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l6376 0.5a high-side driver quad intelligent power switch 0.5 a four independent outputs 9.5 to 35 v supply voltage range internal current limit non-dissipative over-current pro- tection thermal shutdown under voltage lockout with hys- teresys diagnostic output for under volt- age, over temperature and over current external asynchronous reset in- put presettable delay for overcur- rent diagnostic open ground protection immunity against burst transient (iec 801-4) esd protection (human body model 2kv) description this device is a monolithic quad intelligent power switch in multipower bcd technology, for driving inductive, capacitive or resistive loads. diagnostic for cpu feedback and extensive use of electrical protections make this device inherently indis- tructible and suitable for general purpose indus- trial applications. november 1996 powerdip 16+2+2 multipower bcd technology charge pump driver v s v cp + - + - + - + - v s ovc i 1 i 2 i 3 i 4 r diag 220nf 22nf v cp v s v c v p ovt uv on osc off delay on delay c don c doff o 4 o 3 o 2 o 1 gnd d94in076c 1.25v r s short circuit control off osc uv current limit + - block diagram ordering numbers: l6376 (dip L6376PD (pso) powerso20 1/12
absolute maximum ratings (pin numering referred to powerso20 package) symbol pin parameter value unit v s 6 supply voltage (t w < 10ms) 50 v supply voltage (dc) 40 v v s - v out difference between supply voltage and output voltage internally limited v id 16, 17 externally forced voltage -0.3 to 7 v i id externally forced current 1ma i i 12, 13, 14, 15, 18 channel input current (forced) 2ma v i channel input voltage -0.3 to 40 v i out 2, 3, 8, 9 output current (see also i sc ) internally limited v out output voltage internally limited e il energy inductive load (t j =125c); each channel 200 mj p tot power dissipation internally limited v diag 19 external voltage -0.3 to v s +0.7 v i diag externally forced current -10 to 10 ma t op ambient temperature, operating range -25 to 85 c t j junction temperature, operating range (see overtemperature protection) -25 to 125 c t stg storage temperature -55 to 150 c pin connections (top view) v s v cp o 2 o 1 gnd i 1 gnd i 2 i 3 1 3 2 4 5 6 7 8 9 off delay r diag gnd gnd o 4 o 3 v p v c 20 19 18 17 16 14 15 13 12 d93in030b i 4 10 on delay 11 powerdip gnd o1 i1 o3 vp v s vc vcp o2 o4 gnd 10 8 9 7 6 5 4 3 2 13 14 15 16 17 19 18 20 12 1 11 gnd d95in217 i2 i3 on delay i4 off delay r diag gnd powerso20 l6376 2/12
pin description (pin numering referred to powerso20 package). no pins function 6v s positive supply voltage. an internal circuit, monitoring the supply voltage, maintains the ic in off-state until v s reaches 9v or when v s falls under 8.5v. the diagnostic is availlable since v s = 5v. 7v cp switch driver supply. to minimize the output drop voltage, a supply of about 10v higher than v s is required. in order to use the built-in charge pump, connect a filter capacitor from pin1 to pin. the suggested value assures a fast transition and a low supply ripple even in worse condition. using the four channels contemporarily, values less than 68nf have to be avoided. 2, 3, 8, 9 o 1 , o 2 , o 3 , o 4 high side outputs. four independently controlled outputs with built-in current limitation. 1, 10, 11, 20 gnd ground and power dissipating pins. these pins are connected to the bulk ground of the ic, so are useful for heat dissipation. 12,13, 14, 15 i 1 , i 2 , i 3 , i 4 control inputs. four independent control signals. the output is held off until the voltage at the corresponding input pin reaches 1.35v and is turned off when the voltage at the pin goes below 1.15v. 16 on delay programmable on duration in short circuit. if an output is short circuited to ground or carryng a current exceeding the limit, the output is turned-off and the diagnostic activation are delayed. this procedure allows the driving of hard surge current loads. the delay is programmed connecting a capacitor (50pf to 15nf) versus ground with the internal time constant of 1.28 m s/pf. the function can be disabled short circuiting this pin to ground. 17 off delay programmable off duration in short circuit. after the short circuit or overcurrent detection, the switch is held off before the next attempt to switch on again. the delay is programmed connecting a capacitor (50pf to 15nf) versus ground with the internal time constant of 1.28 m s/pf. short circuiting this pin to ground the off delay is 64 times the on delay. 18 r asyncronous reset input. this active low input (with hysteresis), switch off all the outputs independently from the input signal. by default it is biased low. 19 diag diagnostic output. this open drain output reports the ic working condition. the bad condition (as undervoltage, overcurrent, overtemperature) turns the output low. 5v c pump oscillator voltage. at this pin is available the built-in circuitry to supply the switch driver at about 10v higher than v s . to use this feature, connect a capacitor across pin 4 and pin 5. the suggested value assures a fast transition and a minimum output drop voltage even in worse condition. using the four channels contemporarily, values less than 6.8nf have to be avoided. 4v p bootstrapped voltage. at this pin is available the 11v oscillation for the charge pump, at a typical frequency of 200khz. l6376 3/12
electrical characteristics (v s = 24v; t j = -25 to 125 c; unless otherwise specified.) dc operation (pin numering referred to powerso20 package). symbol pin parameter test condition min. typ. max. unit v s 6 supply voltage 9.5 24 35 v v sth uv upperthreshold 8.5 9 9.5 v v shys uv hysteresis 200 500 800 mv i qsc quiescent current outputs on, no load 3 5 ma v il 12,13, 14,15, 18 input low level 0 0.8 v v ih input high level 2 40 v i bias input bias current v i = 0v -5 -1 0 m a v i = 40v 0 5 20 m a v ihys input comparators hysteresis 100 200 400 mv q lim ovt upper threshold 150 c q h threshold hysteresis 20 30 c i sc 2, 3, 8, 9 short circuit current v s =9.5 to 35v; r l =2 w 0.65 0.9 1.2 a output voltage drop i out =500ma ; t j =25 c 320 500 mv i out =500ma ; t j =125 c 460 640 mv i olk output leakage current v o =0v; v i <0.8v 100 m a v cl internal voltage clamp (v s -v o each output) i o =100ma single pulsed t p =300 m s 47 52 57 v v ol low state output voltage v i = v il ; r l = 0.8 1.5 v i dlkg 19 diagnostic output leakage diagnostic off 25 m a v diag diagnostic output voltage drop i diag = 5ma 1.5 v i dch 16, 17 delay capacitors charge current 40 m a l6376 4/12
ac operation (pin numering referred to powerso20 package). symbol pin parameter test condition min. typ. max. unit t r -t f 2, 3, 8, 9 rise or fall time v s = 24v; r l = 47 w r l to ground 3.8 m s t d 12 vs 9 13 vs 8 14 vs 3 15 vs 2 delay time 1 m s dv/dt 2, 3, 8, 9 slew rate (rise and fall edge) v s = 24v; r l = 47 w rise r l to ground fall 3 4 5 7.6 7 10 v/ m s t on 16 on time during short circuit condition 50 pf < c don < 15nf 1.28 m s/pf t off 17 off time during short circuit condition pin 13 grounded 64 t on 50pf < c doff < 15nf 1.28 m s/pf f max maximum operating frequency 25 khz source drain ndmos diode symbol parameter test condition min. typ. max. unit v fsd forward on voltage i fsd = 500ma 1 1.5 v i fp forward peak current t p = 10ms; duty cycle = 20% 1.5 a t rr reverse recovery time i fsd = 500ma; di fsd /dt = 25a/ m s 200 ns t fr forward recovery time 50 ns 50% 50% t d t d t 90% 90% 10% 10% t f t r t v in v out d94in127a 50% 50% switching waveforms v s d94in126a v sth v shys undervoltage comparator hysteresis l6376 5/12
thermal characteristics r th j-pins dip16+2+2 . the thermal resistance is re- ferred to the thermal path from the dissipat- ing region on the top surface of the silicon chip, to the points along the four central pins of the package, at a distance of 1.5 mm away from the stand-offs. r th j-amb1 if a dissipating surface, thick at least 35 m m, and with a surface similar or bigger than the one shown, is created making use of the printed circuit. such heatsinking surface is considered on the bottom side of an horizontal pcb (worst case). r th j-amb2 if the power dissipating pins (the four central ones), as well as the others, have a mini- mum thermal connection with the external world (very thin strips only) so that the dissi- pation takes place through still air and through the pcb itself. it is the same situation of point above, with- out any heatsinking surface created on pur- pose on the board. additional data on the powerdip and the powerso20 package can be found in: application note an467: thermal characteristics of the powerdip 20,24 packages soldered on 1,2,3 oz. copper pcb application note an668: a new high power ic surface mount pack- age: powerso20 power ic packaging from insertion to surface mounting. thermal data symbol parameter dip16+2+2 powerso20 unit r th j-pin thermal resistance, junction to pin 12 C c/w r th j-amb1 thermal resistance, junction to ambient (see thermal characteristics) 40 C c/w r th j-amb2 thermal resistance, junction to ambient (see thermal characteristics) 50 C c/w r th j-case thermal residance junction-case C 1.5 c/w figure 1: printed heatsink l6376 6/12
overtemperature protection (ovt) if the chip temperature exceeds q lim (measured in a central position in the chip) the chip deactivates itself. the following actions are taken: all the output stages are switched off; the signal diag is activated (active low). normal operation is resumed as soon as (typically after some seconds) the chip temperature moni- tored goes back below q lim - q h . the different thresholds with hysteretic behavior assure that no intermittent conditions can be gen- erated. undervoltage protection (uv) the supply voltage is expected to range from 9.5v to 35v, even if its reference value is consid- ered to be 24v. in this range the device operates correctly. below 9.5v the overall system has to be consid- ered not reliable. consequently the supply voltage is monitored continuously and a signal, called uv, is internally generated and used. the signal is on as long as the supply voltage does not reach the upper internal threshold of the v s comparator v sth . the uv signal disappears above v sth . once the uv signal has been removed, the sup- ply voltage must decrease below the lower threshold (i.e. v sth -v shys ) before it is turned on again. the hysteresis v shys is provided to prevent inter- mittent operation of the device at low supply volt- ages that may have a superimposed ripple around the average value. the uv signal switches off the outputs, but has no effect on the creation of the reference voltages for the internal comparators, nor on the continu- ous operation of the charge-pump circuits. diagnostic logic the situations that are monitored and signalled with the diag output pin are: current limit (ovc) in action; there are 4 indi- vidual current limiting circuits, one per each output; they limit the current that can be sunk from each output, to a typical value of 800ma, equal for all of them; under voltage (uv); over temperature protection (ovt). the diagnostic signal is transmitted via an open drain output (for ease of wired-or connection of several such signals) and a low level represents the presence of at least one of the monitored con- ditions, mentioned above. short circuit operation in order to allow normal operation of the other in- puts when one channel is in short cirtuit, an inno- vative non dissipative over current protection (pat- ent pending) is implemented in the device. output current t on t on t off t off time t in this way, the temperature of the device is kept enough low to prevent the intervention of the ther- mal protection (in most of the cases) and so to avoid the shut down of the whole device. if a short circuit condition is present on one out- put, the current limiting circuit puts that channel in linear mode sourcing the i sc current (typically 800 ma) for a time period (t on ) defined by an external capacitor (c don connected to the on delay pin). after that period, if the short circuit condition is still present the output is turned off for another time period (t off ) defined by a second external capacitor (c doff connected to the off delay pin). when also this period is expired: if the short circuit condition is still present the output stays on for the t on period and the se- quence starts again; if the short circuit condition is not present anymore the normal operation of the output is resumed. the t on and t off periods are completely inde- pendent and can be set from 64 m s to 15 ms, us- ing external capacitors ranging from 50 pf to 15 nf (1.28 m s/pf). if the off delay pin is tied to ground (i.e. the c doff capacitor is not used) the t off time period is 64 times the t on period. the diagnostic output (diag) is active when the output is switched off, while it is not active when the output is on (i.e. during the t on period) even if in that period a short circuit condition is present. typical waveforms for short circuit operation are shown in figure 2. if both the on delay and the off delay pins are grounded the non dissipative over current protection is inhibited and the outputs in short cir- cuit remain on until the thermal shutdown switch off the whole device. in this case the short circuit condition is not signalled by the diag pin (that continues to signal the under voltage and over temperature conditions). programmable diagnostic delay the current limiting circuits can be requested to perform even in absence of a real fault condition, for a short period, if the load is of capacitive na- ture or if it is a filament lamp (that exhibits a very low resistance during the initial heating phase). to avoid the forwarding of misleading i.e. short diagnostic pulses in coincidence with the inter- vention of the current limiting circuits when oper- ating on capacitive loads the activation of the diagnostic can be delayed with respect to the in- tervention of one of the current limiting circuits. this delay can be defined by an external capaci- tor (c don ) connected between the on delay pin and ground. reset input an external reset input r (pin 18) is provided to simultaneously switch off all the outputs: this sig- nal (active low) is in effect an asynchronous reset that keeps the outputs low independently from the input signals. for example, this reset input can be used by the cpu to keep the outputs low after a fault condi- tion (signaled by the diag pin). demagnetization of inductive loads the device has four internal clamping diodes able to demagnetize inductive loads. the limitation is the peak power dissipation of the packages, so if the loads are big or if there is the possibility to demagnetize more loads con- temporarly it is necessary to use external de- magnetization circuits. in figures 4 and 5 are shown two topologies for the demagnetization versus ground and versus v s . the breakdown voltage of the external device (v z ) must be chosen considering the minimum in- ternal clamping voltage (v cl ) and the maximum supply voltage (v s ). v i v s v out 100mv d94in131 1.25v 100mv figure 3: input comparator hysteresis l6376 8/12
driver v cp v s ovc o 4 o 3 o 2 o 1 d94in110a r s short circuit control uv current limit v z v s (max) < v z < v cl (min) v s figure 5: external demagnetization circuit (versus v s ) driver v cp v s ovc o 4 o 3 o 2 o 1 d94in109 r s short circuit control uv current limit v z v z < v cl (min) - v s (max) figure 4: external demagnetization circuit (versus ground) l6376 9/12
powerdip 20 package mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.51 0.020 b 0.85 1.40 0.033 0.055 b 0.50 0.020 b1 0.38 0.50 0.015 0.020 d 24.80 0.976 e 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 f 7.10 0.280 i 5.10 0.201 l6376 10/12
e a2 a e a1 pso20mec detail a t d 110 11 20 e1 e2 h x 45 detail a lead slug a3 s gage plane 0.35 l detail b r detail b (coplanarity) gc -c- seating plane e3 b c n n powerso20 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 3.60 0.1417 a1 0.10 0.30 0.0039 0.0118 a2 3.30 0.1299 a3 0 0.10 0 0.0039 b 0.40 0.53 0.0157 0.0209 c 0.23 0.32 0.009 0.0126 d (1) 15.80 16.00 0.6220 0.6299 e 13.90 14.50 0.5472 0.570 e 1.27 0.050 e3 11.43 0.450 e1 (1) 10.90 11.10 0.4291 0.437 e2 2.90 0.1141 g 0 0.10 0 0.0039 h 1.10 l 0.80 1.10 0.0314 0.0433 n10 (max.) s8 (max.) t 10.0 0.3937 (1) "d and e1" do not include mold flash or protrusions - mold flash or protrusions shall not exceed 0.15mm (0.006") l6376 11/12
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously s upplied. sgs- thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1996 sgs-thomson microelectronics C printed in italy C all rights reserved sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the n etherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. l6376 12/12

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